1. Field of the Invention
The present invention relates to a semiconductor device such as a system LSI (Large-Scaled Integration) for reducing power, and more particularly, to a semiconductor device, such as a system LSI, for controlling power so that the power is autonomously decentralized to be reduced, when mounting, on a chip, various IPs (Intellectual Properties) comprising circuit blocks or circuit modules, which have various functions for the system LSI in distributional formats.
2. Description of the Related Art
According to a technique as disclosed in a paper of “Design Challenges of Technology Scaling” in IEEE MICRO, Vol. 19, No. 4, pp. 23–29, 1999 (hereinafter, referred to as a first conventional art), power consumption of chips for microprocessors is greatly increased and many chips having power consumption of 100W or more have been sold after 2000. Further, according to the first conventional art, power consumption caused by a leak current is exponentially increased in accordance with the miniaturization for manufacturing. In particular, power consumption caused by a subthreshold leak current is remarkably increased.
Moreover, according to a technique as disclosed in a paper of “Identifying Defects in Deep-Submicron CMOS ICS” in IEEE SPECTRUM, pp. 66–71, on September, 1996 (hereinafter, referred to as a second conventional art), the miniaturization for manufacturing produces the increase in power consumption caused by a gate leak current and by a junction leak current such as GIDL (Gate-Induced Drain Leakage).
According to the first conventional art, in active power, when a signal amplitude matches a voltage supply, power PAC generated by charge/discharge of the load is proportional to a value of <(operating frequency f)×(load capacitance C)×(supply voltage V)×(supply voltage V)>. Therefore, conventionally, the supply voltage is reduced.
As disclosed in a record of “Subthreshold-Current Reduction Circuits for Multi-Gigabit DRAMS” titled at Symposium, on VLSI Circuits Digest of Technical Papers, pp. 45–46, on May, 1993, there is proposed a method using a power switch, in which a power switch is provided between a power supply line and a circuit, and power consumption PSL caused by the subthreshold leak current is reduced in a standby mode by turning off the power switch (hereinafter, referred to as a third conventional art).
In addition, as disclosed in “50% Active-Power Saving without Speed Degradation Using Standby Power Reduction (SPR) Circuit” titled in the ISSCC Digest of Technical Papers, pp. 318–319, 1995, there is proposed a substrate bias control method in which a subthreshold leak current is reduced in a standby mode by switching voltages of a substrate terminal in an MOS transistor forming a circuit, in an operating mode and a standby mode and also by a threshold voltage of the MOS transistor in the operating mode and the standby mode (hereinafter, referred to as a fourth conventional art).
In addition, as disclosed in “Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETS by Dual Oxide Thickness MTCMOS (Dot-MTCMOS)” titled in “Extended Abstract of the 1999 International Conference on Solid State Devices and Materials, pp. 264–265, 1999, there is proposed a reducing method for power consumption PGL caused by a gate leak current during a standby mode in which a PMOS transistor having a thick oxide film is provided between a circuit comprising an MOS transistor having a thin oxide film and a power supply line, and a power switch is turned off in a standby mode of the circuit (hereinafter, referred to as a fifth conventional art).
In recent years, due to the increase in functions required for chips, the number of MOS transistors (hereinafter, referred to as MOSTs) integrated on the chip and an operating frequency are also increased. In accordance therewith, power PAC caused by charge/discharge of load power is further increased.
According to the first conventional art, the power PAC can be reduced. However, the first conventional art completely cannot correspond to the trend to increase the power PAC. The power PAC can be generally reduced by decreasing the voltage. However, in this case, when a processing speed of the chip is maintained or improved, due to the necessity to set a threshold voltage of the MOST forming the chip to be low and the necessity to make a thickness of a gate oxide film of the MOST thin, the power consumption PSL caused by the subthreshold leak current and the power consumption PGL caused by the gate leak current are exponentially increased.
Although the first conventional art has the above problem, this art is most efficient to reduce the power consumption PAC caused by the charge/discharge of the load current and is widespread. However, as described in the first and second conventional arts, recently, power consumption PSL and PGL are increased for the above reason.
The third and fourth conventional arts propose a method for solving the increase in power consumption PSL and PGL. According to the third and fourth conventional arts, although the power consumption PSL and PGL can be low in a standby mode of the chip, the power consumption PSL and PGL cannot be low in an operating mode of the chip. Consequently, if the levels of the power consumption PSL and PGL caused by the subthreshold leak current and the gate leak current can be unconsidered, as compared with the level of the power PAC caused by the charge/discharge of the load, the consumption power PSL and PGL may be reduced only in the standby mode of the chip in which the level of the power PAC is close to zero. In this case, the third to fifth conventional arts are efficient. However, if the levels of the power consumption PSL and PGL caused by the subthreshold leak current and the gate leak current are substantially higher, as compared with the level of the power PAC caused by the charge/discharge of the load, the power consumption PSL and PGL have a serious effect on the power consumption of the chip in the operating mode and the power consumption cannot be reduced according to the third to fifth conventional art.
For the above reasons, in recent years, the power consumption of the chip, indicated by (PAC+PSL+PGL) is greatly increased.
Further, in future, the system LSI will be designed by using various IPs according to a technique obtained by combining the above first to fifth conventional arts. In this case, preferably, the IPs can be designed without adding a designer. The development of the miniaturization for manufacturing causes the increase in the number of the IPs mounted on a chip having a predetermined area, for example, an (8×8 mm2)-sized chip and, consequently, the system is mounted on the single chip. In this case, the designer can hardly grasp and process the overall system LSI. Therefore, there is needed another system in which each module is operated to be autonomously decentralized and to correspond to the peripheral condition. Further, there is also needed a process for replacing only a specific part in the halfway of a designing process with other designing components, or a process for replacing only one circuit block having a specification different from those of other circuit blocks after designing.